1. Field of the Invention
The present invention relates to an output buffer that includes a complementary metal oxide semiconductor (MOS), and also relates to a semiconductor device having such output buffer.
2. Description of the Related Art
One example of the above-mentioned type of output buffer is an output buffer equipped with voltage mitigation MOS transistors. One voltage mitigation MOS transistor is provided between an output terminal and each p-channel MOS transistor. Also, one voltage mitigation MOS transistor is provided between the output terminal and each n-channel MOS transistor. These voltage mitigation MOS transistors are provided in order to mitigate overshoot and undershoot in an output voltage. The p-channel and n-channel MOS transistors are complementarily turned on/off in response to an input signal. Such output buffer is disclosed in for example Japanese Patent Application Publication (Kokai) 7-66715. In this output buffer, a fixed bias voltage VB is applied to the gate terminal of each of the voltage mitigation transistors to cause the respective transistor to operate as a resistor element. Such a configuration can prevent sharp change of an output current flowing into the output terminal, and reduce overshoot and undershoot in the output voltage.
Recently, there is a commercialized output buffer that is driven at a power-supply voltage within an acceptable range of 3.0 to 3.6 volts.
In this output buffer, when a power-supply voltage of 3.6 volts is applied, the voltage between the gate and source terminals of a voltage mitigation transistor becomes 3.6 minus VB (3.6−VB) volts. As a result, an output current proportional to the square of this 3.6 minus VB volts is generated.
When, on the other hand, a power-supply voltage of 3.0 volts is applied, the voltage between the gate and source terminals of the voltage mitigation transistor becomes 3.0 minus VB volts. As a result, an output current proportional to the square of this 3.0 minus VB volts is generated.
According to such configuration, the output current is considerably lower when the power-supply voltage is 3.0 volts than when the power-supply voltage is 3.6 volts. This causes waveform distortion in an output signal when a heavy load is connected to the output buffer.